Voltage level shifter

ABSTRACT

Disclosed is a voltage level shifter, including a pull-up circuit, a voltage drop circuit and a pull-down circuit. Through the voltage level shifter, an input voltage is transformed into an output voltage having a different level as compared to that of the input voltage. With the voltage drop circuit, voltages received by the pull-down circuit are reduced and thus transistors of thinner gates may be used, effectively improving switching speed of transistors in the pull-down circuit. As such, noise and jiggle of the output voltage are reduced.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention pertains to a circuit. More particularly, thepresent invention pertains to a voltage level shifter.

2. The Prior Arts

For a currently used integrated circuit (IC) system, a core logic unitand an input/output unit therein are generally supplied with differentvoltages. For example, the core logic unit is typically supplied with avoltage of 1.2 volts while the input/output devices with a voltage of3.3 volts in a device fabricated by 0.13 μm manufacturing process. Sincethe voltages supplied to the core logic unit and input/output unit arenot identical to each other, a conversion circuit is required to beprovided between the two units. Such conversion circuit is generallytermed as “voltage level shifter”.

FIG. 1 shows a conventional voltage level shifter. The voltage levelshifter 10 includes PMOS transistors PG1 and PG2, NMOS transistors NG1and NG2 and an inverter INV. Herein, the PMOS transistors PG1 and PG2are regarded as pull-up transistors while the NMOS transistors NG1 andNG2 are regarded as pull-down transistors. Now, assuming a supplyvoltage VccH is 3.3 volts and an input voltage Vin at an input I isbetween 0 and 1.2 volts of rectangular wave. When the input voltage Vintransits from a low level (ex. 0 volt) to a high level (ex. 1.2 volts),the NMOS transistor NG1 is turned on and the PMOS transistor PG2 is alsoturned on since a gate of the PMOS transistor PG2 is driven to lowlevel. Hence, a high level voltage (i0e. 3.3 volt) is presented at anoutput node O of the voltage level shifter 10. Therefore, the voltagelevel shifter 10 is capable of shifting the input voltage Vin (i.e. 1.2volts) into the output voltage Vout (i.e. 3.3 volts). However, since aspecific period is required for a voltage of 0 volt being shifted into1.2 volts, the PMOS and NMOS transistors PG1,PG2,NG1 and NG2 may notfunction as desired in the voltage level shifter 10 when their gatevoltages are too low (lower than a threshold voltage, about 0.8 volts).In addition, during the time when the PMOS transistor PG2 and NMOStransistor NG2 are approaching to on (or off) and off (or on),contribution of the transistors PG2, NG2 on the output voltage Voutcompete. As such, the output voltage Vout is later in speed in reachingthe low level, compared with only either of the PMOS transistor PG2 andNMOS transistor NG2 is present, causing distortion of the output wave.

FIG. 2 is provided to explain such case. When the input voltage Vintransits from the low level to the high level, the output voltage Voutis pulled to the high level after a delay time Tr. Also, when the inputvoltage Vin transits from the high level to the low level, the outputvoltage Vout decreases to the low level after a delay time Tf.

When noises of different levels are present on the input voltage Vin andthus the real input voltage Vin may not be maintained constant,distortion amount caused from the competition varies, leading to a shifton the transition time of the output voltage Vout, which is called“jiggle”. It is generally desirable to reduce such jiggle so as to havea better fidelity of the output wave with respect to the input wave. Inaddition, the output wave may vary as the noise amount on the input wavevaries since the transistors in the voltage level shifter may functiondifferently at this time as compared to that when no noise is present.It is desired to reduce such output wave deviation.

In addition, since the NMOS transistors NG1, NG2 have a high voltage toendure, which is about 2.5 volts at its maximum, the gates thereof haveto be thicker, thus leading to a higher threshold voltage. In this case,the NMOS transistors NG1, NG2 have to have more time to switch from lowto high. Therefore, it is desired to have a thinner gate for thepull-down transistors NG1, NG2 so that they may have a faster switchingspeed.

SUMMARY OF THE INVENTION

A voltage level shifter having reduced noises and jiggle at an outputthereof is provided.

The voltage level shifter includes a pull-up circuit, a voltage dropcircuit and a pull-down circuit. The voltage drop circuit is used toreduce voltages which the pull-down circuit endures, making gatethickness of the pull-down transistors of the pull-down circuit allowedto be reduced.

The voltage level shifter includes a pull-up circuit, a voltage dropcircuit, a path division circuit and a pull-down circuit. The pathdivision circuit isolates a current between the pull-up and pull-downcircuits at a time when an input voltage of the voltage level shiftertransits from one level to the other level. Therefore, competencebetween the pull-up and pull-down circuits does not appear and thusnoise amount and jiggle on an output voltage of the voltage levelshifter are reduced.

The above and other objects, advantages and principle will be furtherexplained below taken from the preferred embodiments with reference tothe accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings disclose an illustrative embodiment of the presentinvention which serves to exemplify the various advantages and objectshereof, and are as follows:

FIG. 1 is a schematic diagram of a conventional voltage level shifter;

FIG. 2 is a schematic diagram of a waveform of the voltage level shiftershown in FIG. 1;

FIG. 3 is a schematic diagram of a voltage level shifter according to anembodiment of the present invention;

FIG. 4 is a schematic diagram of the voltage level shifter according toanother embodiment of the present invention;

FIG. 5 a is a schematic diagram of a main conversion stage of thevoltage level shifter according to still another embodiment of thepresent invention;

FIG. 5 b is a schematic diagram of an input buffer stage of the voltagelevel shifter according to the embodiment, shown in FIG. 5 a of thepresent invention;

FIG. 5 c is a schematic diagram of an output buffer stage of the voltagelevel shifter according to the embodiment, shown in FIG. 5 a of thepresent invention; and

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A voltage level shifter having reduced noises and jiggle at an outputthereof is provided in the invention.

Referring to FIG. 3, a voltage level shifter according to an embodimentof the present invention is shown therein. As shown, the voltage levelshifter 30 includes a pull-up circuit 31, a voltage drop circuit 33 anda pull-down circuit 34. The pull-up circuit 31 has two PMOS transistorsP1 and P2. The voltage drop circuit 33 has four NMOS transistors N1, N2,N3, and N4. The pull-down circuit 34 has two NMOS transistors N5 and N6.In this embodiment, a direct current (DC) voltage V_(PPIN) and a DCvoltage source VDDIN are provided for the voltage level shifter 30. TheNMOS transistors N5 and N6 are connected to ground GND. In thisconfiguration, an input voltage Vin is shifted into an output voltageVout at node NT1. The DC voltage V_(PPIN) is 3.3 volts, the DC voltageV_(DDIN) is 1.2 volts, the input voltage Vin has a rectangular wavebetween 0 and 1.2 volts, and the output voltage Vout is a correspondingwave between 0 and 3.3 volts. In addition, the voltage level shifter 30further includes an inverter INV (not shown) for providing a inversedinput voltage Vinb, the inverse voltage of the input voltage Vin, andoutputting a inversed output voltage Voutb at NT2.

When the input voltage Vin is transiting from high level to low leveland the inversed input Vinb is transiting from low level to high level.At this time, the NMOS transistor NMOS is turned on while the NMOStransistor N6 is turned off. However, such switch is not immediatelyfinished. When a gate voltage of the NMOS transistors N5, N6 do notexceed a threshold voltage (about 0.7 volts), the NMOS transistors N5,N6 can not be turned on or off. At this time, the output voltage Vout istransiting from high level to low level and the PMOS transistor P2 isturned on. On the other hand, the inversed output Voutb is transitingfrom low level to high level and the PMOS transistor P1 is turned off.When the NMOS transistor N5 becomes really turned on, the output Vout isreduced to low, enabling the PMOS transistor P2 to be turned on. On theother hand, when the NMOS transistor N6 is really turned off, theinversed output Voutb is pulled high, enabling the PMOS transistor P1 tobe turned off. Therefore, when the input voltage Vin is at the low level(ex. 0 volt), the output voltage Vout is also at the low level (i.e. 0volt). When the inversed input voltage Vinb is at the high level (ex.1.2 volts), the inverse output voltage Voutb is also at the high level(i.e. 3.3 volts). As such, the purpose of voltage shifting is achieved.

In addition, in the voltage drop circuit 33, the NMOS transistors N1, N2has a thicker gate (corresponding to a threshold voltage about 0.8volts), while the NMOS transistors N3, N4 has a thinner gate(corresponding to a threshold voltage about 0.7 volts). Hence, thevoltage provided by the pull-up circuit 31 is reduced by about 1.5 voltsby the voltage drop circuit 33 when the NMOS transistors N5, N6 areturned off; otherwise, there is no voltage drop when the NMOStransistors N5, N6 are turned on. Consequently, the gate of the NMOStransistors N5, N6 may be thinner and may be turned on by the inputvoltage Vin at an initial stage (when the input voltage Vin is stilllower) when the input voltage Vin transits from low level to high level.Hence, the NMOS transistors N5, N6 may be turned on in a relativelyshort time. Alternatively, the NMOS transistors N1, N2, N3, and N4 mayeach be replaced with a diode (not illustrated) since the diode may alsoprovide a voltage drop, which makes no difference with the NMOStransistors N1, N2, N3, and N4.

Referring to FIG. 4, the voltage level shifter according to anotherembodiment of the present invention is shown therein. In thisembodiment, all elements of and DC voltages supplied for the voltagelevel shifter are the same with those for the embodiment shown in FIG. 3except that a path division circuit 42 is additionally provided. Thepath division circuit 42 is connected between the pull-up circuit 31 andthe voltage drop circuit 33 and for isolating a current path between thepull-up circuit 31 and the pull-down circuit 34. The path divisioncircuit 42 includes PMOS transistors P3 and P4. When the input voltageVin transits from low level to high level, the NMOS transistor N6 isturned on, the PMOS transistor P1 is also turned on and the PMOStransistor P3 is turned off. When the input voltage Vin risessufficiently to turn off the PMOS transistor P3, a current path betweenthe PMOS transistor P1 and the NMOS transistor N5 is isolated. Thus, thePMOS transistor P1 cannot pull up the output voltage Vout any more butthe NMOS transistor N5 keeps pulling down the output voltage Vout. Thatis, the PMOS P1 transistor does not compete with the NMOS transistor N5again when the current path is isolated. At this time, the outputvoltage Vout may be rapidly decreased to low level when the PMOStransistor P3 is turned off. As such, the voltage level shifter may havereduced jiggle of transition time at the output end owing to an unstableinput voltage Vin.

Referring to FIG. 5 a, FIG. 5 b and FIG. 5 c, the voltage level shifteraccording to another embodiment of the present invention is showntherein. In this embodiment, the voltage level shifter 50 is composed ofthe voltage level shifter shown in FIG. 3 and FIG. 4 (FIG. 5 a) and aninput stage buffer circuit 51 (FIG. 5 b) and an output stage buffercircuit 52 (FIG. 5 c). As shown, the input stage buffer circuit 51includes PMOS transistors P5 and P6 and NMOS transistors N7 and N8 andthe output stage buffer circuit 52 includes a first output buffercircuit 52′ and a second output buffer circuit 52″. The first outputbuffer circuit 52′ includes PMOS transistors P7, P8 and NMOS transistorsN9, N10. The second output buffer circuit 52″ includes PMOS transistorsP9, P10 and NMOS transistors N11, N12. In the voltage level shifter 50,the input stage buffer circuit 51 and output stage buffer circuit 52 isprovided to facilitate measurement of the output voltage Vout andinverse output voltage Voutb shown in FIG. 3 and FIG. 4. In the voltagelevel shifter 50, the first input buffer circuit 52′ and second outputbuffer circuit 52″ may be replaced with two inverters connected inseries. As such, a buffered input voltage Vin2 and buffered outputvoltages Voutb and Vout may also be obtained. In addition, the outputvoltage Voutb is obtained from a voltage presented at a node NT2, whichis buffered at the first output buffer circuit 52′. Similarly, theoutput voltage Vout is obtained from a voltage presented at a node NT1,which is buffered at the second output buffer circuit 52″.

Many changes and modifications in the above described embodiment of theinvention can, of course, be carried out without departing from thescope thereof. Accordingly, to promote the progress in science and theuseful arts, the invention is disclosed and is intended to be limitedonly by the scope of the appended claims. For example, the transistorsmentioned above may be replaced with tri-terminal switches. Theessential principle of the invention may also be applied onto a voltagelevel shifter which has a lower output as compared to its input. In thiscase, the voltage drop transistors are not required and the applied DCvoltages should be adjusted in such a manner that the voltage levelshifter may operate properly. In this regard, the scope of the inventionshould be otherwise defined by the claims provided below.

1. A voltage level shifter for shifting a first input voltage to a firstoutput voltage, comprising: a pull-up circuit, applied by a firstvoltage source for pulling up the first output voltage; and a voltagedrop circuit, connected to the pull-up circuit for providing a voltagedrop; and a pull-down circuit, connected between the pull-up circuit andthe voltage drop circuit for pulling down the first input voltage and asecond input voltage, wherein the second voltage is a inverse voltage ofthe first input voltage; wherein the pull-up circuit is connected to thevoltage drop circuit via a first node and a second node for respectivelyoutputs the first output voltage and a second output voltage of thevoltage level shifter, wherein the second output voltage is a inversevoltage of the first output voltage.
 2. The voltage level shifteraccording to claim 1, wherein the pull-up circuit comprises: a firstpull-up transistor having a source connected to the first voltagesource, a drain connected to the voltage drop circuit via the first nodeand a gate connected to the second node for output the second outputvoltage; and a second pull-up transistor having a source connected tothe first voltage source, a drain connected to the voltage drop circuitvia the second node and a gate connected to the first node for outputthe first output voltage.
 3. The voltage level shifter according toclaim 2, wherein the voltage drop circuit comprises a first voltage-droptransistor, a second voltage-drop transistor, a third voltage-droptransistor and a fourth voltage-drop transistor; wherein the firstvoltage-drop transistor has a drain connected to the drain of the firstpull-up transistor via the first node, a gate connected to the firstvoltage source and a source connected to a drain of the thirdvoltage-drop transistor, the second voltage-drop transistor has a drainconnected to the drain of the second pull-up transistor via the secondnode, a gate connected to the first voltage source and a sourceconnected to a drain of the fourth voltage drop transistor; the thirdvoltage-drop transistor has the drain connected to the source of thefirst voltage-drop transistor, a gate connected to a second voltagesource and a source connected to the pull-down circuit; the fourthvoltage-drop transistor has the drain connected to a source of thesecond voltage-drop transistor, a gate connected to the second voltagesource and the source connected to the pull-down circuit.
 4. The voltagelevel shifter according to claim 3, wherein each of the first and secondvoltage-drop transistors is a NMOS transistor with thicker gate whileeach of the third and fourth voltage-drop transistors is a NMOStransistor with thinner gate.
 5. The voltage level shifter according toclaim 3, wherein the pull-down circuit comprises a first pull-downtransistor and a second pull-down transistor; wherein the first pull-uptransistor has a drain connected to the source of the third voltage-droptransistor, a gate receiving the second input voltage and a sourcegrounded; the second pull-up transistor has a drain connected to thesource of the fourth voltage-drop transistor, a gate receiving the firstinput voltage and a source grounded.
 6. The voltage level shifteraccording to claim 5, wherein the pull-down circuit further comprises aninverter for inversing the first input voltage as the second inputvoltage.
 7. The voltage level shifter according to claim 1, furthercomprises a path division circuit connected between the pull-up circuitand the voltage drop circuit for isolating a current path between thepull-up circuit and the pull-down circuit.
 8. The voltage level shifteraccording to claim 7, wherein the path division circuit comprises afirst division transistor and a second division transistor; wherein thefirst division transistor has a source connected to the pull-up circuit,a gate connected to the pull-down circuit for receiving the second inputvoltage, a drain connected to the voltage drop circuit via the firstnode; the second division transistor has a source connected to thepull-up circuit, a gate connected to the pull-down circuit for receivingthe first input voltage and a drain connected to the voltage dropcircuit via the second node.
 9. The voltage level shifter according toclaim 7, further comprising an input stage buffer circuit connectedbetween the path division circuit and the pull-down circuit, and theinput stage buffer circuit comprising a first buffer transistor, asecond buffer transistor, a third buffer transistor and a fourth buffertransistor; wherein a gate of the first buffer transistor and a gate ofthe third buffer transistor are connected to the pull-down circuit forreceiving the first input voltage; a drain of the second buffertransistor and a drain of the fourth buffer transistor are connected tothe path division circuit for receiving a buffered input voltage; asource of the first buffer transistor and a source of the second buffertransistor are biased by the first voltage source; a source of the thirdbuffer transistor and a source of the fourth buffer transistor aregrounded; a gate of the second buffer transistor, a gate of the fourthbuffer transistor, a drain of the first buffer transistor, and a drainof the third buffer transistor are connected to the pull-down circuitfor receiving the second input voltage.
 10. The voltage level shifteraccording to claim 7, further comprising a first output stage buffercircuit connected to the first node for outputting the first outputvoltage, and a second output stage buffer circuit connected to thesecond node for outputting the second output voltage.
 11. The voltagelevel shifter according to claim 10, wherein each of the first outputbuffer circuit and the second output buffer circuit has two seriouslyconnected inverters.
 12. The voltage level shifter according to claim10, wherein each of the first output buffer circuit and the secondoutput buffer circuit comprises a fifth buffer transistor, a sixthbuffer transistor, a seventh buffer transistor and an eighth buffertransistor; wherein a source of the fifth buffer transistors and asource of the sixth buffer transistor are connected to the first voltagesource; a source of the seventh buffer transistor and a source of theeighth buffer transistor are grounded; a drain of the fifth buffertransistor and a drain of the sixth buffer transistor and a source ofthe seventh buffer transistor and a source of the eighth buffertransistor are connected.
 13. The voltage level shifter according toclaim 12, wherein a gate of the fifth buffer transistor and a gate ofthe seventh buffer transistor are connected to the first node, and agate of the sixth buffer transistor and a gate of the eighth buffertransistor are connected for outputting the first output voltage. 14.The voltage level shifter according to claim 12, wherein a gate of thefifth buffer transistor and a gate of the seventh buffer transistor areconnected to the second node; and a gate of the sixth buffer transistorand a gate of the eighth buffer transistor are connected for outputtingthe second output voltage.
 15. A voltage level shifter used to shift aninput voltage into a target voltage and a ground voltage, comprising: afirst circuit, comprising: first level pull-up transistor; a first pathdivision transistor; a first voltage drop transistor; and a first levelpull-down transistor, wherein the first level pull-up transistor, firstpath division transistor, first voltage drop transistor and firstpull-down transistor are successively grounded; a second circuit,comprising: a second level pull-up transistor; a second path divisiontransistor; a second voltage drop transistor; and a second pull-downtransistor, wherein the second level pull-up transistor, second pathdivision transistor, second voltage drop transistor and second pull-downtransistor are successively grounded, a gate of the second pull-uptransistor is connected to a first node, a gate of the first pull-uptransistor is connected to a second node; and a target DC voltageconnected to an end of the first circuit and an end of the secondcircuit nearer the ground to provide a operating voltage and a gatevoltage of the first and second voltage drop transistors, wherein theinput voltage is fed into the voltage level shifter through a gate ofthe first pull-down transistor and a gate of the first path divisiontransistor and an inversed version of the input voltage is fed into thevoltage level shifter through a gate of the second pull-down transistorand a gate of the second path division transistor; wherein the targetoutput voltage is outputted at the second node when the input voltage ishigh and a ground voltage is outputted at the second node when the inputvoltage is low, and wherein the second path division circuit isisolated, the output voltage is not pulled up by the second pull-uptransistor but only pulled down by the second pull-down transistor whenthe input voltage transits from high to low.
 16. The voltage levelshifter according to claim 15, wherein the first node is connectedbetween the first path division transistor and the first pull-downtransistor and the second node is connected between the second pathdivision transistor and the second pull-down transistor.
 17. The voltagelevel shifter according to claim 15, wherein the first circuit furthercomprises a third voltage drop transistor, and the second voltage droptransistor further comprises a fourth voltage drop transistor.
 18. Thevoltage level shifter according to claim 17, wherein the first node isbetween the first path division transistor and the first pull-downtransistor and the second node is between the second path divisiontransistor and the second pull-down transistor.